1. Field of the Invention
The present invention generally relates to the regulation of a voltage across a load. More specifically, the present invention relates to such a regulation performed in linear fashion.
2. Discussion of the Related Art
FIG. 1 partially and schematically illustrates a conventional example of a linear regulator of a voltage Vout across a load (LD) 1. The regulator comprises a P-channel MOS transistor 2 having its source connected to a high voltage supply rail Vdd and having its drain forming output terminal OUT of the regulator. Load 1 is connected between terminal OUT and a low supply or reference voltage rail or ground GND. Transistor 2 operates in linear state, that is, its transconductance is used to vary its output current according to the control voltage applied on its gate G. The control voltage of gate G is regulated according to voltage Vout across load 1. The regulation is performed by a differential comparator 3 comprising an input/output stage 4 and an output stage 5. Input/output stage 4 comprises two differential branches each comprised of a P-channel MOS transistor 61, 62 series-connected with an N-channel MOS transistor 63, 64. The sources of transistors 61 and 62 are connected to an output terminal of a current source 60, an input terminal of which is connected to high supply Vdd. The sources of transistors 63 and 64 are connected to low supply GND. The gates of transistors 63 and 64 are interconnected. A branch 61-63 forms an input branch, while the other branch 62-64 forms an output branch. Transistor 61 of the input branch receives a D.C. constant voltage reference Vreg provided by a voltage generator 8, connected between the gate of transistor 61 and ground GND. The gate of transistor 63 is connected to its drain, that is, also to the drain of transistor 61. The gate of transistor 63 receives voltage Vout across load 1 by a connection to output terminal OUT of the regulator, possibly to an intermediary tap of a resistor bridge. Connection point 65 of the drains of transistors 62 and 64 forms the output of input/output stage 4 of comparator 3.
Output stage 5 is formed of the series connection, between high supply Vdd and low supply GND, of a generally resistive impedance 9 (R) and an N-channel MOS transistor 10. The connection point of impedance 9 and of transistor 10 forms the output terminal of differential comparator 3 connected to gate G of regulation transistor 2. The gate of transistor 10 is connected to point 65 of differential input/output branch 62-64.
The regulator further comprises a generally capacitive impedance (C) 11, intended to stabilize output voltage Vout.
FIGS. 2A-2C illustrate in timing diagrams an example of the variation along time t of reference voltage Vreg across source 8, of output voltage Vout across load 1, and of voltage Vds between the drain and source terminals of transistor 2. At the circuit power-on, at a time t0, constant D.C. voltage generator 8 is validated to provide a steady non-zero nominal regulation reference voltage Vref until a circuit turn-off time t1. Differential comparator 3 then forces, as illustrated in FIG. 2B, output voltage Vout to follow regulation voltage Vreg and to align on reference level Vref. Voltage Vout is then steadily regulated at level Vref by the gate control until time t1 when the circuit is turned off or set to stand-by. This regulation is performed by a control in linear mode of transistor 2, which is used as a variable transconductance, the output current of which depends on the control voltage of gate G.
Applications in which load 1 must be supplied at a voltage level on the order of from 3.3 to 5.5 volts are more specifically considered in the present invention. Such a value is relatively high as compared to the maximum voltage on the order of from 2.4 to 2.8 volts that the components (in particular MOS transistor 2) used in standard integration technological manufacturing processes can stand. However, in off periods of load 1, MOS transistor 2 must stand voltage Vdd across its terminals.
Indeed, as illustrated in FIG. 2C, in off phases of load 1 (Vreg=0, FIG. 2A), that is, before turn-on time t0 and after turn-off time t1, transistor 2 controlling load 1 must stand, between its drain and source terminals, a potential difference Vds equal to supply amplitude Vdd-GND. However, during the operation of load 1 (Vreg=Vref), voltage Vds is reduced to the difference between high supply Vdd and voltage Vout across load 1, that is, nominal regulation value Vref.
To enable transistor 2 to stand the voltage during off phases, the 2.5-volt standard manufacturing process has been modified to insert MOS transistors capable of withstanding a maximum voltage greater than 5 volts between their drain and their source. The masks of definition of regulation transistor 2 have, in particular, been modified with respect to the neighboring transistors, to considerably increase the thickness of a portion of a gate insulator close to one of the drain/source regions and to increase the surface area of this same drain/source region. But then, the stray capacitance of the gate of transistor 2 is increased, and its transconductance is reduced. Now, to enable linear control of transistor 2 such as previously described with sufficiently low control levels, the transconductance must be relatively high. To increase it, the integration surface area of transistor 2 must then be further increased.
The surface area increase results in sometimes having to integrate the control switches outside of the chip in which the rest of the power circuit forming the voltage regulator is formed. Further, account must then be taken of a relatively high stray capacitance as compared to the stray capacitances of the other circuit components. Further, the waste voltage, that is, the difference between regulation voltage Vref and output voltage Vout may not easily be reduced to less than 500 mV. This is particularly disadvantageous in portable devices such as electronic diaries, satellite telephones, portable computers or pocket organizers. Indeed, obtaining the nominal output level necessary to the proper load operation requires using a reference voltage of higher level. This increases the circuit bulk and/or, more generally, then causes an accelerated discharge of the batteries supplying the entire circuit and enabling provision of reference voltage Vref. In this last case, frequent recharges of the device batteries must be performed, which is incompatible with their portable character.
Further, the modifications of the manufacturing process necessary to form the regulation MOS transistor are particularly impairing in terms of complication of the general process and of cost.
To overcome these problems, it has been provided to use a regulation transistor of high-voltage bipolar type, which has the advantage of requiring less integration surface area than the specific MOS transistor, especially because it can more easily be integrated vertically in a silicon substrate. However, the use of a bipolar transistor poses many problems.
Especially, a BiCMOS manufacturing process which is more complex than the MOS manufacturing process must be used. A specific circuit must also be provided to set the operating point of the bipolar transistor, and especially provide a limitation of the base current. Further, a bipolar regulation transistor results in higher waste voltages than a MOS transistor with a more restricted linearity range. This is particularly disadvantageous in the case of devices of portable type for which it is desirable to reduce the waste voltage as much as possible, that is, to make it, preferably, smaller than 200 mV.